WM8946ECSSLASHR datasheet(87/175 Pages) WOLFSON

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Production Data

WM8946

PD, July 2012, Rev 4.3

The video buffer control registers are described in Table 57.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R38 (26h)

Video Buffer

VB_ENA

Video buffer enable

0 = Disabled

1 = Enabled

VB_QBOOST

Video buffer filter Q-Boost control

0 = Disabled

1 = Enabled

VB_GAIN

Video buffer gain

0 = 0dB (=6dB unloaded)

1 = 6dB (=12dB unloaded)

4:3

VB_DISOFF

111

Video buffer DC offset control

000 = Reserved

001 = 40mV offset

010 = Reserved

011 = 20mV offset

100 = Reserved

101 = Reserved

110 = Reserved

111 = 0mV offset

Note – the specified offset applies

to the 0dB gain setting

(VB_GAIN=0). When 6dB gain is

selected, the DC offset is doubled.

VB_PD

Video buffer pull-down

0 = pull-down disabled

1 = pull-down enabled

VB_CLAMP

Enable the clamp between the

video input and ground

0 = no clamp

1 = Video buffer input is clamped to

ground

Table 57 Video Buffer Control

The video buffer circuit is illustrated in Figure 34.

Figure 34 Video Buffer Block Diagram

The video buffer requires two external resistor components, as illustrated in Figure 34. For best

performance, the resistor RSOURCE should be matched (equal) to the load impedance RLOAD.

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