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WM8946ECS/R 데이터시트(PDF) 29 Page - Wolfson Microelectronics plc

부품명 WM8946ECS/R
상세설명  Stereo Low-Power CODEC with Video Buffer
PDF  175 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8946ECS/R 데이터시트(HTML) 29 Page - Wolfson Microelectronics plc

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Production Data
WM8946
w
PD, July 2012, Rev 4.3
29
Figure 12 Digital Microphone Interface Timing
The digital microphone interface control fields are described in Table 6.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
Power
Management 1
7
DMIC_ENA
0
Enables Digital Microphone mode
0 = Audio DSP input is from ADC
1 = Audio DSP input is from digital
microphone interface
When DMIC_ENA = 0, the Digital
microphone clock (DMICCLK) is
held low.
Table 6 Digital Microphone Interface Control
ANALOGUE-TO-DIGITAL CONVERTER (ADC)
The WM8946 uses two 24-bit sigma-delta ADCs. The use of multi-bit feedback and high
oversampling rates reduces the effects of jitter and high frequency noise. The ADC full-scale input
level is proportional to LDOVOUT. See “Electrical Characteristics” section for further details. Any input
signal greater than full scale may overload the ADC and cause distortion.
The ADCs and associated digital record filters are enabled by the ADCL_ENA and ADCR_ENA
register bits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
Power
Management
1
11
ADCR_ENA
0
Right ADC Enable
0 = Disabled
1 = Enabled
ADCR_ENA must be set to 1 when
processing right channel data from
the ADC or Digital Microphone.
10
ADCL_ENA
0
Left ADC Enable
0 = Disabled
1 = Enabled
ADCL_ENA must be set to 1 when
processing left channel data from
the ADC or Digital Microphone.
Table 7 ADC Enable Control



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