WM8946ECSSLASHR datasheet(98/175 Pages) WOLFSON

부품명	WM8946ECS/R

상세설명	Stereo Low-Power CODEC with Video Buffer

PDF	175 Pages

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WM8946

Production Data

PD, July 2012, Rev 4.3

The sequence of signals associated with a single register read operation is illustrated in Figure 36.

Figure 36 Control Interface 2-wire (I2C) Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 64.

Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.

This feature is enabled by default, as noted in Table 63.

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge

Stop Condition

R/W

ReadNotWrite

0 = Write

1 = Read

[White field]

Data flow from bus master to WM8946

[Grey field]

Data flow from WM8946 to bus master

Table 64 Control Interface Terminology

Figure 37 Single Register Write to Specified Address

Figure 38 Single Register Read from Specified Address

WM8946ECS/R 데이터시트(PDF) 98 Page - Wolfson Microelectronics plc