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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8946ECS/R 데이터시트(PDF) 17 Page - Wolfson Microelectronics plc |
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WM8946ECS/R 데이터시트(HTML) 17 Page - Wolfson Microelectronics plc |
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17 / 175 page  Production Data WM8946 w PD, July 2012, Rev 4.3 17 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 2 Master Clock Timing Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25 oC. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Master Clock Timing MCLK cycle time TMCLKY 0.037 s s MCLK duty cycle (= TMCLKH : TMCLKL) 60:40 40:60 AUDIO INTERFACE TIMING MASTER MODE BCLK (Output) ADCDAT LRCLK (Output) t DL DACDAT t DDA t DHT t DST Figure 3 Audio Interface Timing - Master Mode Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25 oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode LRCLK propagation delay from BCLK falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 20 ns DACDAT setup time to BCLK rising edge tDST 20 ns DACDAT hold time from BCLK rising edge tDHT 10 ns |
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