WM8946ECSSLASHR datasheet(118/175 Pages) WOLFSON

118 / 175 page

WM8946

Production Data

PD, July 2012, Rev 4.3

118

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R7 (07h)

Additional

control

VMID_FAST_S

TART

VMID (fast-start) Enable

0 = Disabled

1 = Enabled

VMID_REF_SE

VMID Source Select

0 = LDO supply (LDOVDD)

1 = LDO output (LDOVOUT)

VMID_CTRL

VMID Ratio control

Sets the ratio of VMID to the source selected by

VMID_REF_SEL

0 = 5/11

1 = 1/2

STARTUP_BIA

S_ENA

Start-Up Bias Enable

0 = Disabled

1 = Enabled

BIAS_SRC

Bias Source select

0 = Normal bias

1 = Start-Up bias

6:5

VMID_RAMP

[1:0]

VMID soft start enable / slew rate control

00 = Disabled

01 = Fast soft start

10 = Normal soft start

11 = Slow soft start

VMID_ENA

VMID Enable

0 = Disabled

1 = Enabled

3:0

SR[3:0]

1101

Audio Sample Rate select

0011 = 8kHz

0100 = 11.025kHz

0101 = 12kHz

0111 = 16kHz

1000 = 22.05kHz

1001 = 24kHz

1011 = 32kHz

1100 = 44.1kHz

1101 = 48kHz

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R8 (08h)

FLL Control

12:11

FLL_CLK_REF

_DIV[1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must be divided down

to <=13.5MHz.

For lower power operation, the reference clock can be

divided down further if desired.

WM8946ECS/R 데이터시트(PDF) 118 Page - Wolfson Microelectronics plc

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