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WM8946ECS/R 데이터시트(PDF) 128 Page - Wolfson Microelectronics plc

부품명 WM8946ECS/R
상세설명  Stereo Low-Power CODEC with Video Buffer
PDF  175 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8946ECS/R 데이터시트(HTML) 128 Page - Wolfson Microelectronics plc

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WM8946
Production Data
w
PD, July 2012, Rev 4.3
128
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R27 (1Bh)
Left ADC
Digital Vol
12
ADC_VU
0
ADC Volume Update
Writing a 1 to this bit will cause Left and Right ADC
volume to be updated simultaneously
8
ADCL_MUTE
0
Left ADC Digital Mute
0 = Disable Mute
1 = Enable Mute
7:0
ADCL_VOL
[7:0]
1100_0000 Left ADC Digital Volume
0000_0000 = mute
0000_0001 = -71.625dB
0000_0010 = -71.250dB
…
1100_0000 = 0dB
...
1111_1111 = +23.625dB
Register 1Bh Left ADC Digital Vol
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R28 (1Ch)
Right ADC
Digital Vol
12
ADC_VU
0
ADC Volume Update
Writing a 1 to this bit will cause Left and Right ADC
volume to be updated simultaneously
8
ADCR_MUTE
0
Right ADC Digital Mute
0 = Disable Mute
1 = Enable Mute
7:0
ADCR_VOL
[7:0]
1100_0000 Right ADC Digital Volume
0000_0000 = mute
0000_0001 = -71.625dB
0000_0010 = -71.250dB
…
1100_0000 = 0dB
...
1111_1111 = +23.625dB
Register 1Ch Right ADC Digital Vol
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R29 (1Dh)
DRC Control
1
8
DRC_NG_ENA
0
DRC Noise Gate Enable
0 = Disabled
1 = Enabled
7
DRC_ENA
0
DRC Enable
0 = Disabled
1 = Enabled
2
DRC_QR
1
DRC Quick-release Enable
0 = Disabled
1 = Enabled
1
DRC_ANTICLI
P
1
DRC Anti-clip Enable
0 = Disabled
1 = Enabled
Register 1Dh DRC Control 1



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