AFE4490 datasheet(14/69 Pages) TI

14 / 69 page

±500

±400

±300

±200

±100

100

200

300

400

500

100

150

200

250

TX LED DAC Setting

C021

TX_REF = 0.5V

100

150

200

250

TX LED DAC Setting

Expected + 1%

Actual DAC Current

Expected - 1%

C022

TX Reference Voltage = 0.5V

Pleth Current, uA

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

C015

For each setting RF adjusted for Full-Scale

Output.

Amb Cancellation & stage 2 Gain = 4 used for

Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W & NFB is

calculated using 6.6 u RMS noise.

100

110

120

100

% of Full-Scale LED Current

C016

TX_CTRL_SUP = LED_DRV_SUP = 3V

TX Vref = 0.5V

Pleth Current ( A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

C013

For each setting RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.

Pleth Current, uA

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

C014

For each setting RF adjusted for Full-

Scale Output.

Amb Cancellation & stage 2 Gain = 4

used for Low Pleth currents (0.125uA,

0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W &

NFB is calculated using 6.6 u RMS noise.

AFE4400

SBAS601D – DECEMBER 2012 – REVISED MAY 2013

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless

otherwise noted.

Figure 15. NOISE-FREE BITS vs PLETH CURRENT

Figure 16. NOISE-FREE BITS vs PLETH CURRENT

(PRF = 1200 Hz)

(PRF = 2500 Hz)

Figure 17. NOISE-FREE BITS vs PLETH CURRENT

Figure 18. TRANSMITTER DYNAMIC RANGE

(PRF = 5000 Hz)

(5-Hz BW)

Figure 19. TRANSMITTER DAC CURRENT STEP ERROR

Figure 20. TRANSMITTER CURRENT LINEARITY

(50 mA, Max)

(50-mA Range)

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