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PM0056 데이터시트(PDF) 121 Page - STMicroelectronics |
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PM0056 데이터시트(HTML) 121 Page - STMicroelectronics |
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121 / 156 page ![]() DocID15491 Rev 5 121/156 PM0056 Core peripherals 4.3.3 Interrupt clear-enable registers (NVIC_ICERx) Address offset: 0x00 - 0x0B Reset value: 0x0000 0000 Required privilege: Privileged The ICER0-ICER2 registers disable interrupts, and show which interrupts are enabled. 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 CLRENA[31:16] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 76 54 3 21 0 CLRENA[15:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:0 CLRENA[31:0]: Interrupt clear-enable bits. Write: 0: No effect 1: Disable interrupt Read: 0: Interrupt disabled 1: Interrupt enabled. See Table 41: Mapping of interrupts to the interrupt variables on page 119 for the correspondence of interrupts to each register bit. |
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