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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PM0056 데이터시트(PDF) 124 Page - STMicroelectronics |
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PM0056 데이터시트(HTML) 124 Page - STMicroelectronics |
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124 / 156 page  Core peripherals PM0056 124/156 DocID15491 Rev 5 4.3.6 Interrupt active bit registers (NVIC_IABRx) Address offset: 0x00- 0x0B Reset value: 0x0000 0000 Required privilege: Privileged The IABR0-IABR2 registers indicate which interrupts are active. The bit assignments are: 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 ACTIVE[31:16] r rrrr r r r r r rrrr r r 15 14 13 12 11 10 9 8 76 54 3 21 0 ACTIVE[15:0] r rrrr r r r r r rrrr r r Bits 31:0 ACTIVE[31:0]: Interrupt active flags 0: Interrupt not active 1: Interrupt active See Table 41: Mapping of interrupts to the interrupt variables on page 119 for the correspondence of interrupts to each register bit. A bit reads as 1 if the status of the corresponding interrupt is active or active and pending. |
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