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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PM0056 데이터시트(PDF) 142 Page - STMicroelectronics |
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PM0056 데이터시트(HTML) 142 Page - STMicroelectronics |
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142 / 156 page  Core peripherals PM0056 142/156 DocID15491 Rev 5 4.4.10 Configurable fault status register (SCB_CFSR) Address offset: 0x28 Reset value: 0x0000 0000 Required privilege: Privileged The CFSR is byte accessible. You can access the CFSR or its subregisters as follows: • Access the complete CFSR with a word access to 0xE000ED28 • Access the MMFSR with a byte access to 0xE000ED28 • Access the MMFSR and BFSR with a halfword access to 0xE000ED28 • Access the BFSR with a byte access to 0xE000ED29 • Access the UFSR with a halfword access to 0xE000ED2A. The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. Figure 20. CFSR subregisters Memory Management Fault Status Register 31 16 15 8 7 0 Usage Fault Status Register Bus Fault Status Register UFSR BFSR MMFSR 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DIVBY ZERO UNALI GNED Reserved NOCP INVPC INV STATE UNDEF INSTR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 76 54 3 21 0 BFARV ALID Reserved STK ERR UNSTK ERR IMPRE CIS ERR PRECI S ERR IBUS ERR MMAR VALID Reserved MSTK ERR M UNSTK ERR Res. DACC VIOL IACC VIOL rw rw rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept cleared Bit 25 DIVBYZERO: Divide by zero usage fault When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see Configuration and control register (SCB_CCR) on page 137. 0: No divide by zero fault, or divide by zero trapping not enabled 1: The processor has executed an SDIV or UDIV instruction with a divisor of 0. Bit 24 UNALIGNED: Unaligned access usage fault: Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see Configuration and control register (SCB_CCR) on page 137. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP. 0: No unaligned access fault, or unaligned access trapping not enabled 1: the processor has made an unaligned memory access. Bits 23:20 Reserved, must be kept cleared |
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