PM0056 datasheet(145/156 Pages) STMICROELECTRONICS

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PM0056

Core peripherals

4.4.11

Hard fault status register (SCB_HFSR)

Address offset: 0x2C

Reset value: 0x0000 0000

Required privilege: Privileged

The HFSR gives information about events that activate the hard fault handler.

This register is read, write to clear. This means that bits in the register read normally, but

writing 1 to any bit clears that bit to 0.

Bit 2

Reserved, must be kept cleared

Bit 1

DACCVIOL: Data access violation flag

When this bit is 1, the PC value stacked for the exception return points to the faulting

instruction. The processor has loaded the MMAR with the address of the attempted access.

0: No data access violation fault

1: The processor attempted a load or store at a location that does not permit the operation.

Bit 1

IACCVIOL: Instruction access violation flag

This fault occurs on any access to an XN region.

When this bit is 1, the PC value stacked for the exception return points to the faulting

instruction. The processor has not written a fault address to the MMAR.

0: No instruction access violation fault

1: The processor attempted an instruction fetch from a location that does not permit

execution.

3029

DEBU

G_VT

FORC

Reserved

rc_w1

Reserved

VECT

TBL

Res.

rc_w1

Bit 31

DEBUG_VT:

Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise

behavior is unpredictable.

Bit 30

FORCED: Forced hard fault

Indicates a forced hard fault, generated by escalation of a fault with configurable priority that

cannot be handles, either because of priority or because it is disabled:

When this bit is set to 1, the hard fault handler must read the other fault status registers to find

the cause of the fault.

0: No forced hard fault

1: Forced hard fault.

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