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V62/12615-01XE-R 데이터시트(PDF) 23 Page - Texas Instruments |
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V62/12615-01XE-R 데이터시트(HTML) 23 Page - Texas Instruments |
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23 / 92 page ![]() TX_CLK TX_EN TXD PMD output pair (T/R) T2.7.1 IDLE DATA DP83848-EP www.ti.com SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013 3.5.7 100BASE-TX Transmit Packet Deassertion Timing Figure 3-8. 100BASE-TX Transmit Packet Deassertion Timing xxx PARAMETER DESCRIPTION NOTES(1) MIN TYP MAX UNIT T2.7.1 TX_CLK to PMD Output Pair 100 Mb/s Normal mode 6 bits Deassertion (1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode. Copyright © 2012–2013, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 23 Submit Documentation Feedback Product Folder Links: DP83848-EP |
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