V62SLASH12615-01XE-R datasheet(43/92 Pages) TI1

43 / 92 page

DP83848-EP

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SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

4.7

BIST

The DP83848 incorporates an internal built-in self test (BIST) circuit to accommodate in-circuit testing or

diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths.

BIST testing can be performed with the part in the internal loopback mode or externally looped back using

a loopback cable fixture.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating

a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random

sequence from the PSR_15 bit in the PHYCR. The received data is compared to the generated pseudo-

random data by the BIST linear feedback shift register (LFSR) to determine the BIST pass or fail status.

The pass or fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit

defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs,

the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.

For transmit VOD testing, the packet BIST continuous mode can be used to allow continuous data

transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).

The number of BIST errors can be monitored through the BIST error count in the CDCTRL1 (0x1Bh), bits

[15:8].

CONFIGURATION

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V62/12615-01XE-R 데이터시트(PDF) 43 Page - Texas Instruments