V62SLASH12615-01XE-R datasheet(39/92 Pages) TI1

39 / 92 page

DP83848-EP

www.ti.com

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

A renegotiation request from any entity, such as a management agent, will cause the DP83848 to halt any

transmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the link

partner will go into link fail and normal auto-negotiation resumes. The DP83848 will resume auto-

negotiation after the break_link_timer has expired by issuing FLP bursts.

4.1.5

Enabling Auto-Negotiation via Software

It is important to note that if the DP83848 has been initialized upon power-up as a non-auto-negotiating

device (forced technology), and it is then required that auto-negotiation or re-auto-negotiation be initiated

via software, bit 12 (auto-negotiation enable) of the BMCR must first be cleared and then set for any auto-

negotiation function to take effect.

4.1.6

Auto-Negotiation Complete Time

Parallel detection and auto-negotiation take approximately 2-3 seconds to complete. In addition, auto-

negotiation with next page should take approximately 2-3 seconds to complete, depending on the number

of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to

auto-negotiation.

4.2

Auto-MDIX

When enabled, this function utilizes auto-negotiation to determine the proper configuration for transmission

and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX operation. The

function uses a random seed to control switching of the crossover circuitry. This implementation complies

with the corresponding IEEE 802.3 auto-negotiation and crossover specifications.

Auto-MDIX is enabled by default and can be configured via strap or via PHYCR (0x19h) register, bits

[15:14].

Neither auto-negotiation nor auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.

Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (0x19h) register.

NOTE

Auto-MDIX will not work in a forced mode of operation.

4.3

PHY Address

The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown below.

Table 4-2. PHY Address Mapping

PIN NUMBER

PHYAD FUNCTION

RXD FUNCTION

PHYAD0

COL

PHYAD1

RXD_0

PHYAD2

RXD_1

PHYAD3

RXD_2

PHYAD4

RXD_3

CONFIGURATION

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