V62SLASH12615-01XE-R datasheet(60/92 Pages) TI1

60 / 92 page

.1 µF

10 µF

Pin 23 (PFBOUT)

.1 µF

Pin 18 (PFBIN1)

Pin 37 (PFBIN2)

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

www.ti.com

Table 7-3. 25 MHz Crystal Specification

PARAMETER

MIN

TYP

MAX

UNIT

CONDITION

Frequency

MHz

Frequency tolerance

±50

ppm

Operational temperature

Frequency stability

±50

ppm

1 year aging

Load capacitance

7.4

Power Feedback Circuit

To ensure correct operation for the DP83848, parallel caps with values of 10

μF (Tantalum) and 0.1 μF

should be placed close to pin 23 (PFBOUT) of the device.

Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected to pin 23 (PFBOUT), each pin requires a small

capacitor (.1

μF). See Figure 7-3 for proper connections.

Figure 7-3. Power Feedback Connection

7.5

Power Down and Interrupt

The power down and interrupt functions are multiplexed on pin 7 of the device. By default, this pin

functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR

(0x11h) will configure the pin as an active low interrupt output.

7.5.1

Power Down Control Mode

The PWR_DOWN/INT pin can be asserted low to put the device in a power down mode. This is equivalent

to setting bit 11 (power down) in the basic mode control register, BMCR (0x00h). An external control

signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the

device can be configured to initialize into a power down state by use of an external pulldown resistor on

the PWR_DOWN/INT pin. Since the device will still respond to management register accesses, setting the

INT_OE bit in the MICR register will disable the PWR_DOWN/INT input, allowing the device to exit the

power down state.

7.5.2

Interrupt Mechanisms

The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting

bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be output, dependent on the interrupt mask set in

the lower byte of the MISR (0x12h). The PWR_DOWN/INT pin is asynchronously asserted low when an

interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the

MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the

MISR clears ALL pending interrupts.

DESIGN GUIDELINES

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