V62SLASH12615-01XE-R datasheet(13/92 Pages) TI1

13 / 92 page

DP83848-EP

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SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

Table 2-2. MAC Data Interface (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been

detected within a received packet in 100 Mb/s mode.

RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and RXDV is

asserted in 100 Mb/s mode.

RX_ER

S, O, PU

This pin is not required to be used by a MAC, in either MII or RMII mode, since the Phy is required to corrupt

data on a receive error.

This pin is not used in SNI mode.

MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for

RXD_0

S, O, PD

100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.

RXD_1

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.

RXD_2

SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid

data when CRS is asserted. RXD[3:1] are not used in this mode.

RXD_3

MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.

RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid

CRS/CRS_DV

S, O, PU

indications. For a detailed description of this signal, see the RMII Specification.

SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid

receive data on the RXD_0 signal.

MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit

and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of

approximately 1

μs at the end of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat

COL

S, O, PU

function during 10 Mb/s full duplex operation.

RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS

from the CRS_DV signal and use that along with its TX_EN signal to determine collision.

SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit

and receive activity) in 10 Mb/s SNI mode.

Table 2-3. Clock Interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848 and must be

connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83848 supports either an external crystal

resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1

only.

RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be

connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source.

CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal

resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.

25 MHz CLOCK OUTPUT:

In MII mode, this pin provides a 25 MHz clock output to the system.

25MHz_OUT

In RMII mode, this pin provides a 50 MHz clock output to the system.

This allows other devices to use the reference clock from the DP83848 without requiring additional clock

sources.

OVERVIEW

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