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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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V62/12615-01XE-R 데이터시트(PDF) 28 Page - Texas Instruments |
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V62/12615-01XE-R 데이터시트(HTML) 28 Page - Texas Instruments |
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28 / 92 page  TX_CLK TX_EN PWD output pair PMD output pair 0 0 T2.16.1 T2.16.2 1 1 TX_CLK TX_EN TXD PMD output pair T2.15.2 T2.15.1 DP83848-EP SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013 www.ti.com 3.5.15 10BASE-T Transmit Timing (Start of Packet) Figure 3-16. 10BASE-T Transmit Timing (Start of Packet) xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.15.1 Transmit Output Delay from the 10 Mb/s MII mode 3.5 bits Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the 10 Mb/s Serial mode 3.5 bits Rising Edge of TX_CLK 3.5.16 10BASE-T Transmit Timing (End of Packet) Figure 3-17. 10BASE-T Transmit Timing (End of Packet) xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.16.1 End of Packet High Time (with ‘0’ 250 300 ns ending bit) T2.16.2 End of Packet High Time (with ‘1’ 250 300 ns ending bit) 28 ELECTRICAL SPECIFICATIONS Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP |
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