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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV2501INPGF 데이터시트(PDF) 170 Page - Texas Instruments |
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TNETV2501INPGF 데이터시트(HTML) 170 Page - Texas Instruments |
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170 / 197 page  Electrical Specifications 170 December 2002 − Revised November 2008 SPRS206K Table 5−32. McBSP Transmit and Receive Switching Characteristics†‡ NO. PARAMETER MIN MAX UNIT M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D−1§ D+1§ ns M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C−1§ C+1§ ns M4 td(CKRH–FRV) Delay time, CLKR high to internal FSR valid CLKR int −2 6 ns M4 td(CKRH–FRV) Delay time, CLKR high to internal FSR valid CLKR ext 4 16 ns M5 td(CKXH–FXV) Delay time, CLKX high to internal FSX valid CLKX int 0 6 ns M5 td(CKXH–FXV) Delay time, CLKX high to internal FSX valid CLKX ext 4 16 ns M6 tdis(CKXH–DXHZ) Disable time, CLKX high to DX high impedance CLKX int −5 5 ns M6 tdis(CKXH–DXHZ) Disable time, CLKX high to DX high impedance following last data bit CLKX ext 1 11 ns Delay time, CLKX high to DX valid. CLKX int 6 Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. CLKX ext 16 M7 t Delay time, CLKX high to DX valid¶ DXENA = 0 CLKX int 6 ns M7 td(CKXH–DXV) Delay time, CLKX high to DX valid Only applies to first bit transmitted DXENA = 0 CLKX ext 16 ns Only applies to first bit transmitted when in Data Delay 1 or 2 DXENA = 1 CLKX int 2P+2 when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 CLKX ext 2P+8 Enable time, CLKX high to DX driven¶ DXENA = 0 CLKX int 0 M8 ten(CKXH–DX) Enable time, CLKX high to DX driven Only applies to first bit transmitted DXENA = 0 CLKX ext 6 ns M8 ten(CKXH–DX) Only applies to first bit transmitted when in Data Delay 1 or 2 DXENA = 1 CLKX int 2P ns when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 CLKX ext 2P+6 Delay time, FSX high to DX valid¶ DXENA = 0 FSX int 2 M9 td(FXH–DXV) Delay time, FSX high to DX valid Only applies to first bit transmitted DXENA = 0 FSX ext 7 ns M9 td(FXH–DXV) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) DXENA = 1 FSX int 2P+2 ns when in Data Delay 0 (XDATDLY=00b) mode. DXENA = 1 FSX ext 2P+7 Enable time, FSX high to DX driven¶ DXENA = 0 FSX int 0 M10 ten(FXH–DX) Enable time, FSX high to DX driven Only applies to first bit transmitted DXENA = 0 FSX ext 6 ns M10 ten(FXH–DX) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) DXENA = 1 FSX int 2P ns when in Data Delay 0 (XDATDLY=00b) mode DXENA = 1 FSX ext P+6 † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. § T=CLKRX period = (1 + CLKGDV) * P C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even ¶ See the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592) for a description of the DX enable (DXENA) and data delay features of the McBSP. |
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