TNETV2501INPGF datasheet(166/197 Pages) TI1

166 / 197 page

Electrical Specifications

166

December 2002 − Revised November 2008

SPRS206K

5.14 TIM0/TIM1/WDTOUT Timings

5.14.1

TIM0/TIM1/WDTOUT Timer Pin Timings

Table 5−26 and Table 5−27 assume testing over recommended operating conditions (see Figure 5−28 and

Figure 5−29).

Table 5−26. TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements†

NO.

MIN

MAX

UNIT

tw(TIML)

Pulse width, TIM0/TIM1/WDTOUT low

tw(TIMH)

Pulse width, TIM0/TIM1/WDTOUT high

† P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

Table 5−27. TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

td(COH–TIMH)

Delay time, CLKOUT high to TIM0/TIM1/WDTOUT high‡

td(COH–TIML)

Delay time, CLKOUT high to TIM0/TIM1/WDTOUT low‡

tw(TIM)

Pulse duration, TIM0/TIM1/WDTOUT

P†

† P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

‡ In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

TIM0/TIM1/WDTOUT

as Input

Figure 5−28. TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins

CLKOUT

TIM0/TIM1/WDTOUT

as Output

Figure 5−29. TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins

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