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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD9689-2000EBZ 데이터시트(PDF) 133 Page - Analog Devices |
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AD9689-2000EBZ 데이터시트(HTML) 133 Page - Analog Devices |
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133 / 134 page  Data Sheet AD9689 Rev. A | Page 133 of 134 LAYOUT GUIDELINES The ADC evaluation board can be used as a guide to follow good layout practices. The evaluation board layout is set up in such a way as to • Minimize coupling between the analog inputs (Channel A to Channel B and Channel B to Channel A). • Minimize clock coupling to the analog inputs. • Provide enough power and ground planes for the various supply domains while reducing cross coupling. • Provide adequate thermal relief to the ADC. Figure 159 shows the overall layout scheme used for the AD9689 evaluation boards. AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8) Use AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8) to provide a separate power supply node to the SYSREF± circuits of the AD9689. If running in Subclass 1, the AD9689 can support periodic one-shot or gapped signals. To minimize the coupling of this supply into the AVDD1 supply node, adequate supply bypassing is needed. ADC CH.A CH.B CLK± JESD204B LANES POWER Figure 159. Recommended PCB Layout for the AD9689 |
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