DSP56366P datasheet(24/110 Pages) NXP

24 / 110 page

DSP56366 Technical Data, Rev. 3.1

2-20

Freescale Semiconductor

2.11

SPDIF Transmitter Digital Audio Interface

2.12

Timer

Table 2-13 Digital Audio Interface (DAX) Signals

Signal

Name

Type

State During

Reset

Signal Description

ACI

Input

GPIO

Disconnected

Audio Clock Input—This is the DAX clock input. When programmed to use

an external clock, this input supplies the DAX clock. The external clock

frequency must be 256, 384, or 512 times the audio sampling frequency

(256

× Fs, 384 × Fs or 512 × Fs, respectively).

PD0

Input, output, or

disconnected

GPIO

Disconnected

Port D 0—When the DAX is configured as GPIO, this signal is individually

programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

ADO

Output

GPIO

Disconnected

Digital Audio Data Output—This signal is an audio and non-audio output

in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format.

PD1

Input, output, or

disconnected

GPIO

Disconnected

Port D 1—When the DAX is configured as GPIO, this signal is individually

programmable as input, output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Table 2-14 Timer Signal

Signal

Name

Type

State during

Reset

Signal Description

TIO0

Input or Output

Input

Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an

external event counter or in measurement mode, TIO0 is used as input.

When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0

is used as output.

The default mode after reset is GPIO input. This can be changed to output or

configured as a timer input/output through the timer 0 control/status register

(TCSR0). If TIO0 is not being used, it is recommended to either define it as

GPIO output immediately at the beginning of operation or leave it defined as

GPIO input but connected to Vcc through a pull-up resistor in order to ensure

a stable logic level at this input.

This input is 5 V tolerant.

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