DSP56366P datasheet(64/110 Pages) NXP

64 / 110 page

DSP56366 Technical Data, Rev. 3.1

3-38

Freescale Semiconductor

333

HCS hold time after data strobe deassertion9

—0.0

—

334

Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)

—

4.7

—

335

Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)

—

3.3

—

336

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data

strobe assertion9

• Read

•Write

—0

4.7

—

337

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe

deassertion9

—3.3

—

338

Delay from read data strobe deassertion to host request assertion for “Last

Data Register” read4

, 5, 10

8.3

—

339

Delay from write data strobe deassertion to host request assertion for “Last

Data Register” write5

, 8, 10

× T

16.7

—

340

Delay from data strobe assertion to host request deassertion for “Last Data

, 9, 10

—

19.1

341

Delay from data strobe assertion to host request deassertion for “Last Data

, 9, 10, 11

—

300.0

342

Delay from DMA HACK deassertion to HOREQ assertion

•

For “Last Data Register” read5

•

For “Last Data Register” write5

• For other cases

× T

C + 19.1

1.5

× T

C + 19.1

35.8

31.6

0.0

—

343

Delay from DMA HACK assertion to HOREQ deassertion

•HROD = 05

—

20.2

344

Delay from DMA HACK assertion to HOREQ deassertion for “Last Data

• HROD = 1, open drain Host Request5

, 11

—

300.0

1 See Host Port Usage Considerations in the DSP56366 User’s Manual.

2 In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3 V

CC = 3.3 V ± 0.16 V; TJ = –40°C to +110°C, CL = 50 pF

4 The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.

5 The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.

6 This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers

without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.

7 This timing is applicable only if two consecutive reads from one of these registers are executed.

8 The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

9 The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single

data strobe mode.

10 The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.

11 In this calculation, the host request signal is pulled up by a 4.7 k

Ω resistor in the open-drain mode.

Table 3-18 Host Interface (HDI08) Timing1, 2 (continued)

No.

Characteristics3

Expression

120 MHz

Unit

Min

Max

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