DSP56366P datasheet(46/110 Pages) NXP

46 / 110 page

DSP56366 Technical Data, Rev. 3.1

3-20

Freescale Semiconductor

5 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t

PC equals 3 × TC for

read-after-read or write-after-write sequences).

6 BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

7 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

Table 3-11

DRAM Page Mode Timings, Three Wait States1, 2, 3

No.

Characteristics

Symbol

Expression4

Min

Max

Unit

131 Page mode cycle time for two consecutive accesses of the same

direction

Page mode cycle time for mixed (read and write) accesses

tPC

× T

1.25

× T

40.0

35.0

—

132 CAS assertion to data valid (read)

tCAC

× T

C − 7.0

—

13.0

133 Column address valid to data valid (read)

tAA

× T

C − 7.0

—

23.0

134 CAS deassertion to data not valid (read hold time)

tOFF

0.0

—

135 Last CAS assertion to RAS deassertion

tRSH

2.5

× T

C − 4.0

21.0

—

136 Previous CAS deassertion to RAS deassertion

tRHCP

4.5

× T

C − 4.0

41.0

—

137 CAS assertion pulse width

tCAS

× T

C − 4.0

16.0

—

138 Last CAS deassertion to RAS assertion5

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

tCRP

2.25

× T

C − 6.0

3.75

× T

C − 6.0

4.75

× T

C − 6.0

6.75

× T

C − 6.0

—

41.5

61.5

—

139 CAS deassertion pulse width

tCP

1.5

× T

C − 4.0

11.0

—

140 Column address valid to CAS assertion

tASC

TC − 4.0

6.0

—

141 CAS assertion to column address not valid

tCAH

2.5

× T

C − 4.0

21.0

—

142 Last column address valid to RAS deassertion

tRAL

× T

C − 4.0

36.0

—

143 WR deassertion to CAS assertion

tRCS

1.25

× T

C − 4.0

8.5

—

144 CAS deassertion to WR assertion

tRCH

0.75

× T

C − 4.0

3.5

—

145 CAS assertion to WR deassertion

tWCH

2.25

× T

C − 4.2

18.3

—

146 WR assertion pulse width

tWP

3.5

× T

C − 4.5

30.5

—

147 Last WR assertion to RAS deassertion

tRWL

3.75

× T

C − 4.3

33.2

—

148 WR assertion to CAS deassertion

tCWL

3.25

× T

C − 4.3

28.2

—

149 Data valid to CAS assertion (write)

tDS

0.5

× T

C − 4.0

1.0

—

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