CC1110-RTR1 datasheet(33/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 33 of 202

program memory, 4 KB SRAM and hardware

registers) is described in section 12.3.2.

12.3.1 Memory Map

This section gives an overview of the memory

map.

The memory map showing how the different

physical memories are mapped into the CPU

memory spaces is given in

Figure 7 and Figure 8.

The memory differs from the standard 8051

memory map in two important aspects, as

described below.

First, in order to allow the DMA controller

access to all physical memory and thus allow

DMA transfers between these areas, all the

physical memories are mapped into a unified

XDATA memory space as shown in

Figure 7.

Secondly, the CODE memory space is

mapped so that all physical memory is

mapped to CODE space, by using a unified

mapping of the CODE memory space.

Details about the mapping of all 8051 memory

spaces are given in the next section.

CC2510 XDATA memory space

Physical memory

4 KB SRAM

Hardware radio

registers

XDATA memory space

DATA

memory space

8051 memory spaces

Non-volatile program memory

32 KB

0x0000

Hardware registers

Fast access RAM

0xFF00

Slow access RAM /

program memoryin RAM

0xF000

0xFFFF

0x0000

0x7FFF

0xFF

0x00

Hardware SFR

registers

0xFEFF

0xDF00

0xDF80

0xDFFF

32 KB Flash

0x0000

0xFFFF

0x7FFF

Unimplemented 55 KB

0x8000

0xDEFF

Unimplemented 1 KB

0xE000

0xEFFF

SFR

memory space

0xFF

0x80

Figure 7: CC1110 XDATA memory space

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