CC1110-RTR1 datasheet(93/203 Pages) TI

93 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 93 of 202

for channel 0, T1CTL.CH1IF for channel 1,

and T1CTL.CH2IF for channel 2. An interrupt

request is generated if the corresponding

interrupt

mask

bit

T1CCTL0.IM,

T1CCTL1.IM, or T1CCTL2.IM, respectively,

is set.

Examples of output compare modes in various

timer modes are given in the following figures.

Edge-aligned

PWM output signals can be

generated using the timer modulo mode and

channels 1 and 2 in output compare mode 6 or

7 as shown in Figure 17. The period of the

PWM signal is determined by the setting

T1CC0 and the duty cycle for the channel

output is determined by T1CCn. The timer free-

running mode may also be used. In this case

CLKCON.TICKSPD and the prescaler divider

value T1CTL.DIV set the period of the PWM

signal. The polarity of the PWM signal is

determined by whether output compare mode

6 or 7 is used. PWM output signals can also

be generated using output compare modes 4

and 5 as shown in the same figure, or by using

modulo mode as shown in Figure 17. Using

output compare mode 4 and 5 is preferred for

simple PWM.

Centre-aligned

PWM

outputs

can

generated when the timer up/down mode is

selected. The channel output compare mode 4

or 5 is selected depending on required polarity

of the PWM signal. The period of the PWM

signal is determined by T1CC0 and the duty

cycle for the channel output is determined by

T1CCn.

The centre-aligned PWM mode is required by

certain types of motor drive applications and

typically less noise is produced than the edge-

aligned PWM mode because the I/O pin

transitions are not lined up on the same clock

edge.

In some types of applications, a defined delay

or dead time is required between outputs.

Typically this is required for outputs driving an

H-bridge configuration to avoid uncontrolled

cross-conduction in one side of the H-bridge.

The delay or dead-time can be obtained in the

PWM outputs by using T1CCn as shown in the

following:

Assuming that channel 1 and channel 2 are

used to drive the outputs using timer up/down

mode and the channels use output compare

modes 4 and 5 respectively. If T1CC1 is

greater than T1CC2, then the timer period (in

Timer 1 clock periods) is:

TP = T1CC0 x 2

and the dead time, i.e. the time from when the

channel 1 output goes low until the channel 2

output goes high, (in Timer 1 clock periods) is

given by:

TD = T1CC1 – T1CC2

CC1110-RTR1 데이터시트(PDF) 93 Page - Texas Instruments

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