CC1110-RTR1 datasheet(53/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 53 of 202

IRCON2 (0xE8) – Interrupt Flag 5

Bit

Name

Reset

R/W

Description

7:5

R/W

Not used

WDTIF – Watchdog timer interrupt flag.

Interrupt not pending

WDTIF

R/W

Interrupt pending

P1IF – Port 1 interrupt flag.

Interrupt not pending

P1IF

R/W

Interrupt pending

UTX1IF – USART1 TX interrupt flag.

Interrupt not pending

UTX1IF

R/W

Interrupt pending

UTX0IF – USART0 TX interrupt flag.

Interrupt not pending

UTX0IF

R/W

Interrupt pending

P2IF – Port2 interrupt flag.

Interrupt not pending

P2IF

R/W

Interrupt pending

12.7.3 Interrupt Priority

The interrupts are grouped into six interrupt

priority groups and the priority for each group

is set by the registers IP0 and IP1. In order to

assign a higher priority to an interrupt, i.e. to its

interrupt group, the corresponding bits in IP0

and IP1 must be set as shown in Table 30 on

page 54.

The interrupt priority groups with assigned

interrupt sources are shown in Table 31. Each

group is assigned one of four priority levels.

While an interrupt service request is in

progress, it cannot be interrupted by a lower or

same level interrupt.

In the case when interrupt requests of the

same

priority

level

are

received

simultaneously, the polling sequence shown in

Table 32 is used to resolve the priority of each

request.

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