 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
CC1110-RTR1 데이터시트(PDF) 65 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
CC1110-RTR1 데이터시트(HTML) 65 Page - Texas Instruments |
|
|
65 / 203 page  CC1110 CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A Page 65 of 202 inputs. The state of P2SEL is overridden by the debug interface. Also, the direction is overridden when the chip changes the direction to supply the external host with data. 13.1.7 32.768 kHz XOSC input Ports P2_3 and P2_4 are used to connect an external 32.768 kHz crystal. These port pins will be used by the 32.768 kHz crystal oscillator when CLKCON.OSC32K is low, regardless of register settings. The port pins will be set in analog mode when CLKCON.OSC32K is low. 13.1.8 Unused I/O pins Unused I/O pins should have a defined level and not be left floating. One way to do this is to leave the pin unconnected and configure the pin as a general purpose I/O input with pull-up resistor. This is also the state of all pins during reset. Alternatively the pin can be configured as a general purpose I/O output. In both cases the pin should not be connected directly to VDD or GND in order to avoid excessive power consumption. 13.1.9 IOC registers The registers for the IO ports are described in this section. The registers are: • P0 Port 0 • P1 Port 1 • P2 Port 2 • PERCFG Peripheral control register • ADCCFG ADC input configuration register • P0SEL Port 0 function select register • P1SEL Port 1 function select register • P2SEL Port 2 function select register • P0DIR Port 0 direction register • P1DIR Port 1 direction register • P2DIR Port 2 direction register • P0INP Port 0 input mode register • P1INP Port 1 input mode register • P2INP Port 2 input mode register • P0IFG Port 0 interrupt status flag register • P1IFG Port 1 interrupt status flag register • P2IFG Port 2 interrupt status flag register • PICTL Interrupt mask and edge register • P1IEN Port 1 interrupt mask register P0 (0x80) – Port 0 Bit Name Reset R/W Description 7:0 P0[7:0] 0xFF R/W Port 0. General purpose I/O port. Bit-addressable. P1 (0x90) – Port 1 Bit Name Reset R/W Description 7:0 P1[7:0] 0xFF R/W Port 1. General purpose I/O port. Bit-addressable. P2 (0xA0) – Port 2 Bit Name Reset R/W Description 7:0 - 000 R0 Not used 4:0 P2[4:0] 0x1F R/W Port 2. General purpose I/O port. Bit-addressable. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
