CC1110-RTR1 datasheet(26/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 26 of 202

Figure 5:

CC1110 Block Diagram

A block diagram of

CC1110 is shown in Figure 5.

The modules can be roughly divided into one

of three categories: CPU-related modules,

radio-related modules and modules related to

power, test and clock distribution. In the

following subsections, a short description of

each module that appears in Figure 5 is given.

9.1

CPU and Peripherals

The 8051 CPU core is a single-cycle 8051-

compatible core. It has three different memory

access

buses

(SFR,

DATA

and

CODE/XDATA), a debug interface and an 18-

input extended interrupt unit. See section 12

for details.

The memory crossbar/arbitrator is at the

heart of the system as it connects the CPU

and

DMA

controller

with

the

physical

memories and all peripherals through the SFR

bus. The memory arbitrator has four memory

access points, access at which can map to

one of three physical memories: a 4 KB

SRAM, 32 KB flash memory or SFR registers.

The memory arbitrator is responsible for

performing

arbitration

and

sequencing

between simultaneous memory accesses to

the same physical memory.

The SFR bus is drawn conceptually in the

block diagram as a common bus that connects

all hardware peripherals to the memory

arbitrator. The SFR bus also provides access

to the radio registers in the radio register bank

even though these are indeed mapped into

XDATA memory space.

The 4 KB SRAM maps to the DATA memory

space and part of the XDATA/CODE memory

spaces. The memory is an ultra-low-power

SRAM that retains its contents even when the

digital part is powered off (power modes 2 and

3).

The 32 KB flash block provides in-circuit

programmable non-volatile program memory

for the device and maps into the CODE and

XDATA memory spaces. Writing to the flash

block is performed through a flash controller

that allows page-wise (1024 byte) erasure and

byte-wise reprogramming. See section 13.14

for details.

A versatile five-channel DMA controller is

available in the system and accesses memory

using a unified memory space (XDATA) and

thus has access to all physical memories.

Each channel is configured (trigger, priority,

transfer mode, addressing mode, source and

destination pointers, and transfer count) with

DMA descriptors anywhere in memory. Many

of the hardware peripherals rely on the DMA

controller for efficient operation (AES core,

flash write controller, USARTs, Timers, ADC

interface)

performing

data

transfers

between

single

SFR

address

and

flash/SRAM. See section 13.2 for details.

The interrupt controller services 18 interrupt

sources, divided into six interrupt groups, each

of which is associated with one of four interrupt

priorities. An interrupt request is serviced even

if the device is in a sleep mode (power modes

1-3) by bringing the

CC1110 back to active

mode (power mode 0).

The debug interface implements a proprietary

two-wire serial interface that is used for in-

circuit

debugging.

Through

this

debug

interface it is possible to perform an erasure of

the entire flash memory, control which

oscillators are enabled, stop and start

execution of the user program, execute

supplied instructions on the 8051 core, set

code breakpoints, and single step through

instructions

the

code.

Using

these

techniques, it is possible to elegantly perform

in-circuit

debugging

and

external

flash

programming. See section 12.9 for details.

The I/O-controller is responsible for all

general-purpose I/O pins. The CPU can

configure whether peripheral modules control

certain pins or whether they are under

software control, and if so whether each pin is

configured as an input or output and if a pull-

up or pull-down resistor in the pad is

connected. Each peripheral that connects to

the I/O-pins can choose between two different

locations to ensure flexibility in various

applications. See section 13.1 for details.

The sleep timer is an ultra-low power timer

that counts 32.768 kHz crystal oscillator or

32.768 kHz RC oscillator periods. The sleep

timer runs continuously in all operating modes

except power mode 3. It can be configured in

one of several resolution modes, to strike the

right balance between timer resolution and

timeout period. Typical uses for it is as a real-

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