CC1110-RTR1 datasheet(80/203 Pages) TI

80 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 80 of 202

13.2.2 DMA Configuration Parameters

Setup and control of the DMA operation is

performed by the user software. This section

describes the parameters that must be

configured before a DMA channel can be

used. Section 13.2.3 on page 82 describes

how the parameters are set up in software and

passed to the DMA controller.

The behavior of each of the five DMA channels

is configured with the following parameters:

Source address

. The first address from which

the DMA channel should read data.

Destination address

. The first address to

which the DMA channel should write the data

read from the source address. The user must

ensure that the destination is writable.

Transfer count

. The number of transfers to

perform before rearming or disarming the DMA

channel and alerting the CPU with an interrupt

request. The length can be defined in the

configuration or it can be defined as described

next as VLEN setting.

VLEN setting.

The DMA channel is capable of

variable length transfers using the first byte or

word to set the transfer length. When doing

this, various options regarding how to count

number of bytes to transfer are available.

Priority

. The priority of the DMA transfers for

the DMA channel in respect to the CPU and

other DMA channels and access ports.

Trigger event

. All DMA transfers are initiated

by so-called DMA trigger events. This trigger

either starts a DMA block transfer or a single

DMA transfer. In addition to the configured

trigger, a DMA channel can always be

triggered

setting

its

designated

DMAREQ.DMAREQx flag. The DMA trigger

sources are described in Table 37 on page 84.

Source and Destination Increment.

The

source and destination addresses can be

controlled to increment, decrement, or not

change, in order to give good flexibility for

various types of transfers.

Transfer

mode.

The

transfer

mode

determines whether the transfer should be a

single transfer or a block transfer, or repeated

versions of these.

Byte or word transfers.

Determines whether

each DMA transfer should be 8-bit (byte) or

16-bit (word).

Interrupt Mask.

An interrupt request is

generated upon completion of the DMA

transfer. The interrupt mask bit controls if the

interrupt generation is enabled or disabled.

M8:

Decide whether to use seven or eight bits

of length byte for transfer length. Only

applicable when doing byte transfers.

A detailed description of all configuration

parameters is given in the following sections.

13.2.2.1 Source Address

The address of the location in XDATA memory

space where the DMA channel shall start to

read data for the transfer.

13.2.2.2 Destination Address

The address of the location in XDATA memory

space where the DMA channel shall start to

write transfer data. The user must ensure that

the destination is writable.

13.2.2.3 Transfer Count

The number of bytes/words needed to be

transferred for the DMA transfer to be

complete. When the transfer count is reached,

the DMA controller rearms or disarms the DMA

channel and alerts the CPU with an interrupt

request. The transfer count can be defined in

the configuration or it can be defined as a

variable length described in the next section.

13.2.2.4 VLEN Setting

The DMA channel is capable of using the first

byte or word (for word, bits 12:0 are used) in

source data as the transfer length. This allows

variable length transfers. When using variable

length transfer, various options regarding how

to count number of bytes to transfer is given.

In any case, the LEN setting is used as

maximum transfer count. Note that the M8 bit

is only used when byte size transfers are

chosen.

Options are:

1. Default

Transfer

number

bytes/words

commanded

first

byte/word

(transfers

length

byte/word,

and

then

many

bytes/words as dictated by length

byte/word)

2. Transfer

number

bytes/words

commanded by first byte/word

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