CC1110-RTR1 datasheet(45/203 Pages) TI

45 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 45 of 202

Instruction

ADD

ADDC

SUBB

MUL

DIV

RRC

RLC

SETB C

CLR C

CPL C

ANL C,bit

ANL C,/bit

ORL C,bit

ORL C,/bit

MOV C,bit

CJNE

“0”=set to 0, “1”=set to 1, “x”=set to 0/1, “-“=not affected

Table 28: Instructions that affect flag settings

12.7 Interrupts

The CPU has 18 interrupt sources. Each

source has its own request flag located in a set

of Interrupt Flag SFR registers. Each interrupt

requested by the corresponding flag can be

individually

enabled

disabled.

The

definitions of the interrupt sources and the

interrupt vectors are given in Table 29.

The interrupts are grouped into a set of priority

level groups with selectable priority levels.

The interrupt enable registers are described in

section 12.7.1 and the interrupt priority settings

are described in section 12.7.3 on page 53.

12.7.1 Interrupt Masking

Each interrupt can be individually enabled or

disabled by the interrupt enable bits in the

Interrupt Enable SFRs IEN0, IEN1 and IEN2.

The Interrupt Enable SFRs are described

below and summarized in Table 29.

Note that some peripherals have several

events that can generate the interrupt request

associated with that peripheral. This applies to

Port 0, Port 1, Port 2, DMA, Timer 1, Timer 3 ,

Timer 4 and Radio. These peripherals have

interrupt mask bits for each internal interrupt

source in the corresponding SFR registers.

In order to use any of the interrupts in the

CC1110 the following steps must be taken

1. Enable global interrupt by setting the

EA bit in IEN0 to 1

2. Set

the

corresponding

individual

interrupt enable bit in the IEN0, IEN1

or IEN2 register to 1.

3. Set individual interrupt enable bit in

the peripherals SFR register, if any.

4. Begin the interrupt service routine at

the corresponding vector address of

that interrupt. See Table 29 for

addresses.

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