CC1110-RTR1 datasheet(78/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 78 of 202

13.2 DMA Controller

The

CC1110 includes a direct memory access

(DMA) controller, which can be used to relieve

the 8051 CPU core of handling data

movement operations. Thus the

CC1110 can

achieve high overall performance with good

power efficiency. The DMA controller can

move data from a peripheral unit such as ADC

or RF transceiver to memory with minimum

CPU intervention.

The DMA controller module coordinates all

DMA transfers, ensuring that DMA requests

are prioritized appropriately relative to each

other and CPU memory access. The DMA

controller contains a number of programmable

DMA channels for memory-to-memory data

movement.

The DMA controller controls data movement

over the entire XDATA memory space. Since

the SFR registers are mapped into the DMA

memory space these flexible DMA channels

can be used to unburden the 8051 in

innovative ways, e.g. feed a USART with data

from memory, periodically transfer samples

between ADC and memory, produce a desired

I/O waveform by transferring a pattern in

memory to an I/O port output register, etc. Use

of the DMA can also reduce system power

consumption by keeping the CPU in a low-

power mode without having to wake up to

move data to or from a peripheral unit.

The main features of the DMA controller are as

follows:

•

Five independent DMA channels

•

Three configurable levels of DMA

channel priority

•

30 configurable transfer trigger events

•

Independent control of source and

destination address

•

Single, block and repeated transfer

modes

•

Supports variable transfer length by

including the length field in the transfer

data

•

Can operate in either word-size or

byte-size mode

13.2.1 DMA Operation

There are five DMA channels available in the

DMA controller numbered channel 0 to

channel 4. Each DMA channel can move data

from one place within the DMA memory space

to another.

In order to use a DMA channel it must first be

configured as described in sections 13.2.2 and

13.2.3.

Once a DMA channel has been configured it

must be armed before any transfers are

allowed to be initiated. A DMA channel is

armed by setting the appropriate bit in the

DMA Channel Arm register DMAARM.

When a DMA channel is armed a transfer will

begin when the configured DMA trigger event

occurs. There are 30 possible DMA trigger

events, e.g. UART transfer, Timer overflow

etc. The trigger event to be used by a DMA

channel

set

the

DMA

channel

configuration. The DMA trigger events are

listed in Table 37.

In addition to starting a DMA transfer through

the DMA trigger events, the user software may

force a DMA transfer to begin by setting the

corresponding DMAREQ bit.

Figure 10 shows the DMA state diagram.

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