CC1110-RTR1 datasheet(34/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 34 of 202

Physical memory

4 KB SRAM

Hardware radio

registers

Non-volatile program memory

32 KB

0x0000

Hardware registers

Fast access RAM

0xFF00

Slow access RAM /

program memoryin RAM

0xF000

0x7FFF

Hardware SFR

registers

0xDF00

0xDF80

0xDFFF

Unimplemented

55 KB

0x8000

0xDEFF

32 KB Flash

0x7FFF

0x0000

0xFFFF

Unimplemented

0xE000

0xEFFF

Figure 8: CODE memory space

12.3.2 Memory Space

This section describes the details of each CPU

memory space.

XDATA memory space. The 32 KB flash

program memory is mapped into the address

range 0x0000-0x7FFF, the 4 KB SRAM into

address range 0xF000-0xFFFF, radio registers

into address range 0xDF00-0xDF3D and the

SFR registers into address range 0xDF80-

0xDFFF. This allows the DMA controller (and

the CPU) access to all the physical memories

in a single unified address space. One of the

ramifications of this mapping is that the first

address of usable SRAM starts at address

0xF000 instead of 0x0000, and therefore

compilers/assemblers must take this into

consideration.

In low-power modes PM2-3, the 4 KB SRAM

at XDATA address range 0xF000-0xFFFF will

retain its contents. Refer to section 13.10 on

page 130 for a detailed description of power

modes and SRAM data retention.

CODE memory space. The mapping of the

CODE memory space is similar to the XDATA

mapping with the exception that SFR registers

internal to the CPU can not be accessed.

These SFR registers are shown in grey in

Table 25. Since XDATA and CODE memory

accesses share a common bus on the CPU,

their memory spaces are made similar to

simplify memory decoding. The 4 KB SRAM is

included in the CODE address space to allow

program execution out of the SRAM.

DATA memory space. The 8-bit address

range of DATA memory is mapped into the

upper 256 bytes of the 4 KB SRAM. This area

is also accessible through the CODE and

XDATA memory spaces at the address range

0xFF00-0xFFFF.

SFR memory space. The 128-entry hardware

space. The SFR registers are also accessible

through the XDATA/DMA address space at the

address range 0xDF80-0xDFFF. Some CPU-

specific SFR registers reside inside the CPU

core and can only be accessed using the SFR

memory space and not through the duplicate

mapping into XDATA memory space.

12.3.3 Data Pointers

The

CC1110 has two data pointers, DPTR0 and

DPTR1 to accelerate the movement of data

blocks to/from memory. The data pointers are

generally used to access CODE or XDATA

space e.g.

MOVC A,@A+DPTR

MOV A,@DPTR.

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