CC1110-RTR1 datasheet(92/203 Pages) TI

92 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 92 of 202

0000h

T1CC0

overflow

Figure 15 : Up/down mode

13.3.6 Channel Mode Control

The channel mode is set with each channel’s

control and status register T1CCTLn. The

settings include input capture and output

compare modes.

13.3.7 Input Capture Mode

When a channel is configured as an input

capture channel, the I/O pin associated with

that channel, is configured as an input. After

the timer has been started, a rising edge,

falling edge or any edge on the input pin will

trigger a capture of the 16-bit counter contents

into the associated capture register. Thus the

timer is able to capture the time when an

external event takes place.

Note: before an I/O pin can be used by the

timer, the required I/O pin must be configured

as a Timer 1 peripheral pin as described in

section 13.1.4 on page 62 .

The channel input pin is synchronized to the

internal system clock. Thus pulses on the input

pin must have a minimum duration greater

than the system clock period.

The content of the 16-bit capture register is

read out from registers T1CCnH:T1CCnL.

When the capture takes place the interrupt flag

for

the

channel

set.

This

bit

T1CTL.CH0IF for channel 0, T1CTL.CH1IF

for channel 1, and T1CTL.CH2IF for channel

2. An interrupt request is generated if the

corresponding

interrupt

mask

bit

T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM,

respectively, is set.

13.3.7.1 RF Event Capture

Each timer channel may be configured so that

an RF interrupt RFIF event will trigger a

capture instead of the normal input pin

capture. This function is selected with the

use either the input pin or the RFIF interrupt as

capture event. When RFIF is selected as

capture input, the interrupt source(s) enabled

by RFIM (see section 15.3.1 on page 156) will

trigger a capture. In this way the timer can be

used to capture a value when e.g. a start of

frame delimiter (SFD) is detected.

13.3.8 Output Compare Mode

In output compare mode the I/O pin associated

with a channel is set as an output. After the

timer has been started, the contents of the

counter is compared with the contents of the

channel compare register T1CCnH:T1CCnL. If

the compare register equals the counter

contents, the output pin is set, reset or toggled

according to the compare output mode setting

of T1CCTLn.CMP. Note that all edges on

output pins are glitch-free when operating in a

given output compare mode. Writing to the

compare register T1CCnL is buffered so that a

value written to T1CCnL does not take effect

until the corresponding high order register,

T1CCnH is written. For output compare modes

1-3, a new value written to the compare

registers have been written. For other output

compare modes the new value written to the

compare register take effect when the timer

reaches 0x0000.

Note that channel 0 has fewer output compare

modes than channel 1 and 2 because

T1CC0H:T1CC0L has a special function in

modes 6 and 7, meaning these modes would

not be useful for channel 0.

When a compare occurs, the interrupt flag for

the channel is set. This bit is T1CTL.CH0IF

CC1110-RTR1 데이터시트(PDF) 92 Page - Texas Instruments

CC1110-RTR1 데이터시트(HTML) 92 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL