CC1110-RTR1 datasheet(128/203 Pages) TI

128 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 128 of 202

Result c = encrypted message(m) + U

Message Decryption

CCM Mode decryption

the

coprocessor,

the

automatic

generation of CTR works on 32 bits,

therefore the maximum length of a

message is 128 x 2

32 bits, that is 236 bytes,

which can be written in a six-bit word. So,

the value L is set to 6. To decrypt a CCM

mode processed message, the following

sequence can be conducted (key is

already loaded):

Message Parsing Phase

(1)

The software parses the message by

separating the M rightmost octets, namely

U, and the other octets, namely string C.

(2)

C is padded with zeros until it can fill

an integer number of 128-bit blocks;

(3)

U is padded with zeros until it can fill a

128-bit block.

(4)

The software creates the key stream

block A0. It is done the same way as for

CCM encryption.

(5)

The software loads A0 by selected a

Load IV/Nonce command. To do so, it sets

Mode to CFB or OFB at the same time it

selects the IV load.

(6)

The software calls a CFB or an OFB

encryption on the encrypted authenticated

data U. The uploaded buffer contents stay

unchanged (M=16), or only its first M bytes

stay unchanged, the others being set to 0

(M!=16). The result is T.

(7) The software calls a CTR mode

decryption right now on the encrypted

message blocks C. It does not have to

reload the IV/CTR.

Reference

Authentication

tag

generation

This

phase

identical

the

Authentication Phase of CCM encryption.

The only difference is that the result is

named MACTag (instead of T).

Message

Authentication

checking

Phase

The software compares T with MACTag.

13.9.6 Sharing the AES coprocessor

between layers

The AES coprocessor is a common

resource shared by all layers. The AES

coprocessor can only be used by one

instance one at a time. It is therefore

necessary to implement some kind of

software semaphore to allocate and de-

allocate the resource.

13.9.7 AES Interrupts

The AES interrupt, ENC, is produced

when encryption or decryption of a block is

completed. The interrupt enable bit is

IEN0.ENCIE and the interrupt flag is

S0CON.ENCIF.

13.9.8 AES DMA Triggers

There are two DMA triggers associated

with the AES coprocessor. These are

ENC_DW which is active when input data

needs to be downloaded to the ENCDI

when output data needs to be uploaded

from the ENCDO register.

The ENCDI and ENCDO registers should be

set as destination and source locations for

DMA channels used to transfer data to or

from the AES coprocessor.

13.9.9 AES Registers

The AES coprocessor registers have the

layout shown in this section.

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