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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HCS08 데이터시트(PDF) 105 Page - Motorola, Inc |
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HCS08 데이터시트(HTML) 105 Page - Motorola, Inc |
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105 / 290 page  Data Sheet — MC9S08GB60/D V1.5 MOTOROLA 105 MC9S08GB/GT LOCRE — Loss of Clock Reset Enable The LOCRE bit determines how the system handles a loss of clock condition. 1 = Generate a reset request on loss of clock. 0 = Generate an interrupt request on loss of clock. RFD — Reduced Frequency Divider The RFD bits control the value of the divider following the clock select circuitry. The value specified by the RFD bits establishes the division factor (R) applied to the selected output clock source. Writes to the RFD bits will not take effect if a previous write is not complete. Table 6-8 MFD Multiplication Factor Select MFD Value Multiplication Factor (N) 000 4 001 6 010 8 011 10 100 12 101 14 110 16 111 18 Table 6-9 RFD Reduced Frequency Divider Select RFD Division Factor (R) 000 ÷1 001 ÷2 010 ÷4 011 ÷8 100 ÷16 101 ÷32 110 ÷64 111 ÷128 |
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