HCS08 datasheet(107/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

107

MC9S08GB/GT

LOCS — Loss Of Clock Status

The LOCS bit is an indication of ICG loss of clock status.

1 = ICG has lost clock since LOCS was last cleared, LOCRE determines action taken.

0 = ICG has not lost clock since LOCS was last cleared.

ERCS — External Reference Clock Status

The ERCS bit is an indication of whether or not the external reference clock (ICGERCLK) meets the

minimum frequency requirement.

1 = External reference clock is stable, frequency requirement is met.

0 = External reference clock is not stable, frequency requirement is not met.

ICGIF — ICG Interrupt Flag

The ICGIF read/write flag is set when an ICG interrupt request is pending. It is cleared by a reset or

by reading the ICG status register when ICGIF is set and then writing a logic 1 to ICGIF. If another

ICG interrupt occurs before the clearing sequence is complete, the sequence is reset so ICGIF would

remain set after the clear sequence was completed for the earlier interrupt. Writing a logic 0 to ICGIF

has no effect.

1 = An ICG interrupt request is pending.

0 = No ICG interrupt request is pending.

6.5.4 ICG Status Register 2 (ICGS2)

Figure 6-15 ICG Status Register 2 (ICGS2)

DCOS — DCO Clock Stable

The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error has not

changed by more than nunlock for two consecutive samples and the DCO clock is not static. This bit is

used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It

is also used in self-clocked mode to determine when to start monitoring the DCO clock. This bit is

cleared upon entering the off state.

1 = DCO clock is stable.

0 = DCO clock is unstable.

Bit 7

654321

Bit 0

Read:

0000000

DCOS

Write:

Reset:

00000000

= Unimplemented or Reserved

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