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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HCS08 데이터시트(PDF) 210 Page - Motorola, Inc |
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HCS08 데이터시트(HTML) 210 Page - Motorola, Inc |
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210 / 290 page  Inter-Integrated Circuit (IIC) Module MC9S08GB/GT 210 MOTOROLA 13.2.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • START signal • Slave address transmission • Data transfer • STOP signal The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Figure 13-3. Figure 13-3 IIC Bus Transmission Signals 13.2.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 13-3, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. SCL SDA START SIGNAL ACK BIT 123 4567 8 MSB LSB 123 4567 8 MSB LSB STOP SIGNAL NO SCL SDA 123 456 7 8 MSB LSB 1 2 5 678 MSB LSB REPEATED 34 99 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 CALLING ADDRESS READ/ DATA BYTE AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W NEW CALLING ADDRESS 99 XX ACK BIT WRITE START SIGNAL START SIGNAL ACK BIT CALLING ADDRESS READ/ WRITE STOP SIGNAL NO ACK BIT READ/ WRITE |
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