HCS08 datasheet(214/290 Pages) MOTOROLA

214 / 290 page

Inter-Integrated Circuit (IIC) Module

MC9S08GB/GT

214

MOTOROLA

13.4.3 Arbitration Lost Interrupt

The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more

masters try to control the bus at the same time, the relative priority of the contending masters is determined

by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration

process and the ARBL bit in the status register is set.

Arbitration is lost in the following circumstances:

•

SDA sampled as a low when the master drives a high during an address or data transmit cycle.

•

SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive

cycle.

•

A START cycle is attempted when the bus is busy.

•

A repeated START cycle is requested in slave mode.

•

A STOP condition is detected when the master did not request it.

This bit must be cleared by software by writing a one to it.

13.5 IIC Registers and Control Bits

This section consists of the IIC register descriptions in address order.

Refer to the direct-page register summary in the Memory section of this data sheet for the absolute address

assignments for all IIC registers. This section refers to registers and control bits only by their names. A

Motorola-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

13.5.1 IIC Address Register (IICA)

Figure 13-5 IIC Address Register (IICA)

ADDR — IIC Address Register

The ADDR contains the specific slave address to be used by the IIC module. This is the address the

module will respond to when addressed as a slave.

Bit 7

654321

Bit 0

Read:

ADDR

Write:

Reset:

00000000

= Unimplemented or Reserved

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