HCS08 datasheet(123/198 Pages) NXP

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Internal Clock Source (S08ICSV1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

123

9.1.2

Features

Key features of the ICS module are:

•

Frequency-locked loop (FLL) is trimmable for accuracy

— 0.2% resolution using internal 32 kHz reference

— 2% deviation over voltage and temperature using internal 32 kHz reference

•

Internal or external reference clocks up to 5 MHz can be used to control the FLL

— 3 bit select for reference divider is provided

•

Internal reference clock has 9 trim bits available

•

Internal or external reference clocks can be selected as the clock source for the MCU

•

Whichever clock is selected as the source can be divided down

— 2 bit select for clock divider is provided

– Allowable dividers are: 1, 2, 4, 8

– BDC clock is provided as a constant divide by 2 of the DCO output

•

Control signals for a low power oscillator as the external reference clock are provided

— HGO, RANGE, EREFS, ERCLKEN, EREFSTEN

•

FLL engaged internal mode is automatically selected out of reset

9.1.3

Modes of Operation

There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.

9.1.3.1

FLL Engaged Internal (FEI)

In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL

which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.

9.1.3.2

FLL Engaged External (FEE)

In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an

external reference clock. The BDC clock is supplied from the FLL.

9.1.3.3

FLL Bypassed Internal (FBI)

In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is

bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied

from the FLL.

9.1.3.4

FLL Bypassed Internal Low Power (FBILP)

In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock

derived from the internal reference clock. The BDC clock is not available.

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