HCS08 datasheet(124/198 Pages) NXP

124 / 198 page

Internal Clock Source (S08ICSV1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

124

Freescale Semiconductor

9.1.3.5

FLL Bypassed External (FBE)

In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is

bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock

can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external

clock source. The BDC clock is supplied from the FLL.

9.1.3.6

FLL Bypassed External Low Power (FBELP)

In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock

derived from the external reference clock. The external reference clock can be an external crystal/resonator

supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is

not available.

9.1.3.7

Stop (STOP)

In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled

or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.

9.1.4

Block Diagram

Figure 9-2 is the ICS block diagram.

Figure 9-2. Internal Clock Source (ICS) Block Diagram

DCO

Filter

RDIV

TRIM

/ 2

External Reference

IREFS

Clock Source

Block

CLKS

n=0-7

/ 2n

n=0-3

/ 2n

Internal

Reference

Clock

BDIV

ICSLCLK

ICSOUT

ICSIRCLK

EREFS

RANGE

EREFSTEN

HGO

Optional

IREFSTEN

ICSERCLK

Internal Clock Source Block

ICSFFCLK

ERCLKEN

IRCLKEN

DCOOUT

FLL

RDIV_CLK

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