HCS08 datasheet(125/198 Pages) NXP

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Internal Clock Source (S08ICSV1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

125

9.2

External Signal Description

There are no ICS signals that connect off chip.

9.3

9.3.1

ICS Control Register 1 (ICSC1)

432

CLKS

RDIV

IREFS

IRCLKEN

IREFSTEN

Reset:

Figure 9-3. ICS Control Register 1 (ICSC1)

Table 9-1. ICS Control Register 1 Field Descriptions

Field

Description

7:6

CLKS

Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency

depends on the value of the BDIV bits.

Output of FLL is selected.

Internal reference clock is selected.

External reference clock is selected.

Reserved, defaults to 00.

5:3

RDIV

Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits.

Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.

000 Encoding 0 — Divides reference clock by 1 (reset default)

001 Encoding 1 — Divides reference clock by 2

010 Encoding 2 — Divides reference clock by 4

011 Encoding 3 — Divides reference clock by 8

100 Encoding 4 — Divides reference clock by 16

101 Encoding 5 — Divides reference clock by 32

110 Encoding 6 — Divides reference clock by 64

111 Encoding 7 — Divides reference clock by 128

IREFS

Internal Reference Select — The IREFS bit selects the reference clock source for the FLL.

1 Internal reference clock selected

0 External reference clock selected

IRCLKEN

Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as

ICSIRCLK.

1 ICSIRCLK active

0 ICSIRCLK inactive

IREFSTEN

Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock

remains enabled when the ICS enters stop mode.

1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before

entering stop

0 Internal reference clock is disabled in stop

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