301020013 datasheet(40/109 Pages) AMSOSRAM

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Dragster

Functional description

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DS000444 • v5-00 • 2025-Aug-29

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Figure 22: Pipelined integration timing

Below is an example timing for Dragster sensor operating in interleaved mode, for a fixed line

period.

Figure 23: Dragster interleaved integration timing, for a fixed line period

To ensure accurate sensor performance and preserve image quality, compliance with the

following timing constraints and guidelines is required.

Reset Timing:

•

RST_CVC pulse width must always be fixed at 1 µs.

•

RST_CDS pulse width must always be fixed at 2 µs.

•

The interval between the RST_CVC failing edge and RST_CDS falling edges must always

be fixed at 1 µs.

•

The rising edges of the next reset cycle (RST_CVC and RST_CDS) must occur no earlier

than ≥ 7 clock cycles after SAMPLE falling edge.

Integration Timing:

•

Integration time is defined as the interval between RST_CDS falling edge and SAMPLE

falling edge.

Reset

CVC

Reset

CDS

Integration I

Reset

CVC

Reset

CDS

Integration I+1

Reset

CVC

Reset

CDS

Integration I+2

Conversion I

Conversion I+1

Sample

Start AD

Start

Readout

Readout I

Scan I

Scan I+1

Scan I+2

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