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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H5GQ1H24AFR-R0C 데이터시트(PDF) 63 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C 데이터시트(HTML) 63 Page - Hynix Semiconductor |
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63 / 173 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 63 H5GQ1H24AFR 5. OPERATION 5.1. COMMANDS Notes: 1) H = Logic High Level; L = Logic Low Level; X = Don’t care: signal may be H or L, but not floating 2) Addresses shown are logical addresses; physical addresses are inverted when address bus inversion (ABI) is activated and ABI#=L 3) BA0‐BA3 provide the Mode Register address (MRA), A0‐A11 the opcode to be loaded 4) BA0‐BA3 provide the bank address (BA), A0‐A11 (A12) provide the row address (RA). 5) BA0‐BA3 provide the bank address, A0‐A5 (A6) provide the column address (CA); no sub‐word addressing within a burst of 8. 6) The command is Refresh when CKE#(n) = L and Self Refresh Entry when CKE#(n) = H. 7) BA0‐BA3 and CA are used to select burst location and data respectively 8) DESELECT and NOP are functionally interchangeable 9) In address training mode READ is decoded from the commands pins only with RAS# = H, CAS# = L, WE# = H Table 16 Truth Table ‐ Commands Operation Symbol CKE# CS# RAS# CAS# WE# BA A11 A10 A8 A6, A7, A9, (A12) A0‐ A5 (A6) Notes Previous cycle Current cycle DESELECT (NOP) DES L X H X X X XXX X X X 1, 2, 8 NO OPERATION (NOP) NOP L X L H H H XXX X X X 1, 2, 8 MODE REGISTER SET MRS L L L L L L MRA Opcode 1, 2, 3 ACTIVE (Select bank & activate row) ACT L L L L H H BA RA 1, 2, 4 READ (Select bank and column, & start burst) RD L L LH LH BA LLL X CA 1, 2, 5, 9 READ with Autoprecharge RDA L L L H L H BA L L H X CA 1, 2, 5 Load FIFO LDFF L L LH LH X H LL X X 1, 2, 7 READ Training RDTR L L LH LH X H H L X X 1, 2 WRITE without Mask (Select bank and column, & start burst) WOM L L L H L L BA LLL X CA 1, 2, 5 WRITE without Mask with Autoprecharge WOMA L L LH L L BA LL H X CA 1, 2, 5 WRITE with single‐byte mask WSM L L L H L L BA L H L X CA 1, 2, 5 WRITE with single‐byte mask with Autoprecharge WSMA L L L H L L BA L H H X CA 1, 2, 5 WRITE with double‐byte mask (WDM) WDM L L L H L L BA H L L X CA 1, 2, 5 WRITE with double‐byte mask with Autoprecharge WDMA L L L H L L BA H L H X CA 1, 2, 5 WRITE Training WRTR L L L H L L X H H L X X 1, 2 PRECHARGE (Deactivate row in bank or banks) PRE L L L L H L BA X X L X X 1, 2 PRECHARGE ALL PREALL L L L L H L X X X H X X 1, 2 REFRESH REF L L L L L H XXX X X X 1, 6 POWER DOWN ENTRY PDE L H H X X X XXX X X X 1 L H H H XXX X X X 1 POWER DOWN EXIT PDX H L H X X X XXX X X X 1 LHH H SELF REFRESH ENTRY SRE L H L L L H XXX X X X 1, 6 SELF REFRESH EXIT SRX H L H X X X XXX X X X 1 LHH H |
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