H5GQ1H24AFR-R0C datasheet(56/173 Pages) HYNIX

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H5GQ1H24AFR-R0C 데이터시트(PDF) 56 Page - Hynix Semiconductor

부품명	H5GQ1H24AFR-R0C

상세설명	1Gb (32Mx32) GDDR5 SGRAM

PDF	173 Pages

Scroll/Zoom	100%

제조업체	HYNIX [Hynix Semiconductor]

홈페이지	http://www.skhynix.com/kor/main.do

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56 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Low Power Modes (LP2, LP3)

Bits A1‐A2 control several low power modes of the GDDR5 SGRAM. The modes are independent of each

other.

When bit A1 (LP2) is set, the WCK receivers may be turned off during power‐down.

When bit A2 (LP3) is set, RDTR, WRTR and LDFF commands are not allowed while a REF command is

being executed.

PLL Bandwidth

The PLL bandwidth may optionally be configured to match system characteristics. Each setting defines a

unique combination of ‐3dB corner frequency, peaking frequency and peaking magnitude.

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