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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H5GQ1H24AFR-R0C 데이터시트(PDF) 53 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C 데이터시트(HTML) 53 Page - Hynix Semiconductor |
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53 / 173 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 53 H5GQ1H24AFR The EDC hold pattern will not be transmitted when the device is in address training mode, in WCK2CK training mode, in RDQS mode, in self refresh mode, in reset state, in power‐down state with the LP2 bit set, or in scan mode. With register bit A11 set High, EDC1 and EDC3 will transmit the inverted EDC hold pattern, resulting in a pseudo‐differential pattern. Please note that this function is not available in x16 configuration. Bit A11 is ignored for READ, WRITE and RDTR CRC bursts and the clock phase information in WCK2CK training mode. CRC Write Latency (CRCWL) The value of the CRC write latency is loaded into register bits A4‐A6. If the DRAM vendor does not support the Mode Register definition of CRCWL, the Mode Register settings will be ignored. In that case the valid fixed latency is given with the DRAM vendor’s specification. The user must set the CRCWL Mode Register bits. Speed Allowable Operating Frequency (Gbps) CRCWL14 CRCWL13 CRCWL12 CRCWL11 CRCWL10 CRCWL9 CRCWL8 6.0Gbps 5.5Gbps 5.0Gbps 4.5Gbps 4.0Gbps CRC Read Latency (CRCRL) The value of the CRC read latency is loaded into register bits A7‐A8. If the DRAM vendor does not support the Mode Register definition of CRCRL, the Mode Register settings will be ignored. In that case the valid fixed latency is given with the DRAM vendor’s specification. The user must set the CRCRL Mode Register bits. Speed RDBI ON/OFF Allowable Operating Frequency (Gbps) CRCRL3 CRCRL2 CRCRL1 CRCRL0 6.0Gbps OFF ON 5.5Gbps OFF ON 5.0Gbps OFF ON 4.5Gbps OFF ON 4.0Gbps OFF ON |
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