H5GQ1H24AFR-R0C datasheet(67/173 Pages) HYNIX

부품명	H5GQ1H24AFR-R0C

상세설명	1Gb (32Mx32) GDDR5 SGRAM

PDF	173 Pages

Scroll/Zoom	100%

제조업체	HYNIX [Hynix Semiconductor]

홈페이지	http://www.skhynix.com/kor/main.do

Logo

67 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

The row remains active until a PRECHARGE command (or READ or WRITE command with Auto Pre‐

charge) is issued to the bank.

Figure 38. Active Command

Figure 39. Bank Activation Command Cycle

A8‐A11 (A12)

A0, A1,A6,A7

LOW

RA = Row Address

CA = Column Address

BA = Bank Address

Row Activation

CS#

WE#

CAS#

RAS#

CKE#

DONʹT CARE

BA0‐BA3

A2‐A5

BA0,1,2,3

A2,3,4,5

A8,9,10,11, (12)

A0,1,6,7

CK#

CMD

ADDR

RA RA

BA CA

RA RA

tRCD

tRP

tRAS

tRC

BA = bank address; RA = row address; CA = column address

tRCD = tRCDRD, tRCDWR, tRCDRTR, tRCDWTR or tRCDLTR, depending on command

(*) = could also be PREALL

NOP

ACT

NOP

RD/WR

NOP

PRE*

NOP

ACT

NOP

Donʹt Care

Ta0

Ta1

Tb0

Tb1

Tc1

Tc0

H5GQ1H24AFR-R0C 데이터시트(PDF) 67 Page - Hynix Semiconductor

H5GQ1H24AFR-R0C 데이터시트(HTML) 67 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL