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H5GQ1H24AFR-R0C 데이터시트(PDF) 79 Page - Hynix Semiconductor

부품명 H5GQ1H24AFR-R0C
상세설명  1Gb (32Mx32) GDDR5 SGRAM
PDF  173 Pages
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제조업체  HYNIX [Hynix Semiconductor]
홈페이지  http://www.skhynix.com/kor/main.do
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H5GQ1H24AFR-R0C 데이터시트(HTML) 79 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
79
H5GQ1H24AFR
 5.8. WRITE DATA MASK (DM)
The traditional method of using a DM pin for WRITE data mask must be abandoned for a new method. 
Due to the high data rate of GDDR5 SGRAMs, bit errors are expected on the interface and are not recover‐
able when they occur on the traditional DM pin.
In GDDR5 the DM is sent to the SGRAM over the address following the bank/column address cycle associ‐
ated with the command, during the NOP/DESELECT commands between the WRITE command and the 
next command. The DM is used to mask the corresponding data according to the following table.
Two additional WRITE commands that augment the traditional WRITE Without Mask (WOM) are 
required for proper DM support:
•WDM: WRITE‐With‐Doublebyte‐Mask: 
2 cycle command where the 1st cycle carries address information and the 2nd cycle carries data mask 
information (2 byte granularity);
Table 17: DM State
FUNCTION
DM 
Value
DQ
Write Enable
0
Valid
Write Inhibit
1
X



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