H5GQ1H24AFR-R0C datasheet(44/173 Pages) HYNIX

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H5GQ1H24AFR-R0C 데이터시트(PDF) 44 Page - Hynix Semiconductor

부품명	H5GQ1H24AFR-R0C

상세설명	1Gb (32Mx32) GDDR5 SGRAM

PDF	173 Pages

Scroll/Zoom	100%

제조업체	HYNIX [Hynix Semiconductor]

홈페이지	http://www.skhynix.com/kor/main.do

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44 / 173 page

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

WRITE Recovery (WR)

The programmed WR value is used for the auto precharge feature along with tRP to determine tDAL. The

WR register bits are not a required function and may be implemented at the discretion of the DRAM

manufacturer.

WR must be programmed with a value greater than or equal to RU{tWR/tCK}, where RU stands for round

up, tWR is the analog value from the vendor datasheet and tCK is the operating clock cycle time.

By default WR is specified by bits A8‐A11, defining a WR range of 4 to 19 tCK.

Test Mode

The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to

’0’, and bits A0‐A6 and A8‐A11 set to the desired values. Programming bit A7 to ‘1’ places the device into a

test mode that is only to be used by the DRAM manufacturer. No functional operation is specified with test

mode enabled.

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