H5GQ1H24AFR-R0C datasheet(52/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

4.5. MODE REGISTER 4 (MR4)

Mode Register 4 defines the Error Detection Code (EDC) features of GDDR5 SGRAMs as shown in

Figure 28.

The register is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=0, BA2=1

and BA3=0. Bits A0‐A3 (EDC Hold Pattern) of this register are initialized with ’1111’.

Figure 28. Mode Register 4 (MR4) Definition

EDC Hold pattern / EDC13 Invert

The 4‐bit EDC hold pattern is considered a background pattern transmitted on the EDC pins. The register

is initialized with all ’1’s. The pattern is shifted from right to left and repeated with every clock cycle. The

output timing is the same as of a READ burst.

CRC bursts calculated from WRITEs or READs will replace the EDC hold pattern for the duration of

those bursts, provided CRC is enabled for those bursts.

With each MRS command to MR4 that changes bits A0‐A3 or A9‐A11, the EDC hold pattern will be

undefined for tMRD.

EDC Hold Pattern

000

Pattern

...

111

Pattern

Burst

Pos 3

Burst

Pos 2

Burst

Pos 1

Burst

Pos 0

BA3 BA2 BA1 BA0

A12

A11

A10

EDC

13Inv

CRC

CRC Read

Latency

(CRCRL)

CRC Write Latency

(CRCWL)

EDC Hold Pattern

CRC Write Latency (CRCWL)

N/A

CRC Read Latency (CRCRL)

A10

WR CRC

0On

1Off

RD CRC

0On

1Off

A11

EDC Hold Pattern Invert

for EDC1 + EDC3

EDC hold pattern not

inverted

1EDC hold pattern inverted

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