H5GQ1H24AFR-R0C datasheet(27/173 Pages) HYNIX

27 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 12: EDC pin Behaviour for WCK2CK Training (assumes ‘1111’ as EDC Hold Pattern)

The ideal alignment is indicated by the phase detector output transitioning from “early” to “late” when

the delay of the WCK phase is continuously increased. The WCK phase range for ideal alignment is speci‐

fied by the parameter tWCK2CKPIN ; the value(s) vary with the PLL mode (on or off) and the selected align‐

ment point.

If enabled, the PLL shall not interfere in the behavior of the WCK2CK training. Significantly moving the

phase and/or stopping the WCK during training may disturb the PLL. It is required to perform a PLL reset

after the WCK2CK training has determined and selected the proper alignment between WCK and CK

clocks. The PLL lock time tLK must be met before exiting WCK2CK training to guarantee that the PLL is in

lock such that the GDDR5 SGRAM data synchronizers are set upon WCK2CK training exit.

WCK2CK training is exited via MRS by resetting bit A4 in MR3. For proper reset of the data synchronizers

it is required that the WCK and CK clocks are aligned within tWCK2CKSYNC at the time of the WCK2CK

training exit.

Table 11 Phase Detector and EDC Pin behavior

WCK/2 value sampled by CK

WCK2CK Phase

Data on EDC Pin

Action

‘1’

‘Early’

EDC hold (‘1111’)

Increase Delay on WCK

‘0’

‘Late’

Inverted EDC Hold (‘0000’)

Decrease Delay on WCK

EDC0

WCK01/2

WCK23/2

(internal)

EDC2

‐ tWCK2CK

tWCKTPH

WCK Early

EDC0

WCK01/2

WCK23/2

(internal)

EDC2

+ tWCK2CK

tWCKTPH

WCK Late

1 1 1 1

0 0 0 0

EDC0

WCK01/2

WCK23/2

(internal)

EDC2

tWCKTPH

Aligned

Late

Early

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